1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to semiconductor devices having a plurality of aligned standard cells.
2. Description of the Background Art
In recent years, layout design using a standard cell library is generally performed in system on chip (SOC) because of increasing scale of circuit integration. As the advanced functions and performances of SOC are achieved, the demand for higher integration and higher speeds of the standard cell library increases. On the other hand, an increase in consumption current involved in such achievement of high speeds makes an increasing problem of causing characteristic degradation due to power supply noise such as IR-Drop (i.e., assuming that when current I flows through a path and the resistance value of the path is R, a potential difference represented as I×R is generated at both ends of the path).
Conventionally, there is a configuration of forming, e.g., a complementary metal oxide semiconductor (CMOS) inverter as a function element in a standard cell of a standard cell library. In this configuration, a p-channel MOS transistor (hereinafter referred to as a “pMOS transistor”) is formed on the surface of an n-type well region, and an n-channel MOS transistor (hereinafter referred to as an “nMOS transistor”) is formed on the surface of a p-type well region. Connected to each of these pMOS transistor and nMOS transistor are power supply lines (VDD interconnect and GND interconnect). Each of these power supply lines is connected to a substrate to fix the substrate potential, and is provided commonly in a function element in each standard cell.
Since consumption current of a standard cell increases with increasing speeds of a standard cell library, current flowing through a power supply line also increases. Current of a plurality of standard cells is flowed into a power supply line common to the standard cells. This causes an increase of a value of current that flows through the power supply line, and therefore an effect of IR-Drop needs to be considered. IR-Drop of a power supply line is correlated with the resistance value of the power supply line; the smaller the resistance value is, the smaller the effect of IR-Drop becomes. Therefore, measures to increase the line width of a power supply line have been taken.
On the other hand, with achievement of higher integration of a standard cell library, two CMOS transistors having different drain nodes are sometimes arranged in one standard cell. In this case, a method has been implemented that four transistors are arranged in a row in a vertical direction, as viewed from a plane, to achieve higher integration of a standard cell. With this method, there has been a tendency that the number of interconnects of connecting transistors and the number of interconnects of connecting transistors and power supply lines are increased to make the interconnect layout complicated.
A conventional layout of arranging a plurality of standard cells is disclosed in, e.g., Japanese Patent Laying-Open No. 2000-223575. This patent document discloses that first layer power supply lines (3VDD1 and 3VSS1) and third layer power supply lines (3VDD3 and 3VSS3) in parallel thereto are provided and a signal line (3S2) passes through a second layer, so that the first layer power supply lines are reinforced by the third layer power supply lines without imposing restrictions on the arrangement of the second layer.
However, it has been difficult for such a conventional configuration as mentioned above to include both a configuration of widening power supply lines for higher speeds and a configuration of arranging a plurality of transistors in the vertical direction for higher integration so as to realize a standard cell with higher integration and higher speeds. The reason is that widening of power supply lines makes it difficult to secure intervals between interconnects of connecting drains of a pMOS transistor and an nMOS transistor constituting an inverter and an interconnect portion of connecting the power supply line to the transistor.